PROPOSING A MECHANISM AND INTERNAL DESIGN OF SYNCHRONOUS COUNTERS FOR DISPLAYING DECIMAL VALUES ON SEVEN SEGMENT DISPLAYS

In this paper, J-K Flip Flops are used to design modulus 65 synchronous counter by showing only decimal values rather than ordinary Hexadecimal values. The entire circuit could be designed by cascading two counters together while the ones digit counter provides clock pulses to the tens digit counter. Implementation and design of the counter w as made by using Electronics Workbench software. Partial decoding mechanism is practical to clear each counter in its desired state as well as clear the entire circuit after the number 65 in decimal. TTL Logic (Vcc) was used to provide digital input 1 and Ground to provide digital input 0. The outputs are shown through decoded seven segment displays. The proposed mechanism is practical and applicable to design any modulus counter to show the output in decimal. Furthermore, this mechanism can have advantages over direct modulus counters because the decimal numbers greater than 9 cannot be shown on decoded seven segment displays