EXPLOITING DESIGN OF SYNCHRONOUS COUNTERS METHOD TO DESIGN AND IMPLEMENT MOD 6 DIRECT DOWN COUNTER

In this paper, the design of direct mod 6 down counter is proposed by using J-K Flip Flop. The counter is provided with synchronous clock pulse. The counter is implemented by using Electronic Work bench software. The design can be achieved by the logical function minimization using Karnaugh map. Vcc and Ground are used for inputs to indicate logic 1 and 0 respectively as well as LED indicators are used to indicate the output bits. The proposed design is practical to implement any modul us of direct down counters which can count from any number to zero.