COVERAGE DRIVEN VERIFICATION OF I2C PROTOCOL USING SYSTEM VERILOG

The rapid advances in the integration technologies, enables fabrication of millions of transistors in single IC/Chip. So as the design grows, the verification techniques are required to meet the correctness of the design without exercising exhaustive input - output combination. This paper accommodates reusability of I2C protocol under various test environmen ts, by the following System Verilog which support the complexities of the SoC designs. Here, The RTL Design of I2C is obtained from Opencore.org and its functional verification is carried by self, using System verilog completely wrap DUT.The whole verifica tion done using system verilog Hardware description and Verification language(HDVL), simulated on Questa Sim 10.0b. The concept of seed is used to control the quality of random number generator (RNG) algorithm to run the same test case. The functional cove rage found using Constraint random verification(C RV) approach is 100% and code coverage found is 86.88% & for DUT 93%.