IMPLEMENTATION OF POWER EFFICIENT PROGRAMMABLE PRPG USING BS - LFSR BASED ON BIST

This paper describes a low - power programmable generator with bit swapping technique which is capable of producing pseudorandom test patterns with toggle selection(TOSE) , enhanced fault coverage and power optimization compared to present BIST with normal LFSR based Pseudorandom pattern generator. It consists of a BS - LF SR driving a phase shifter with features like producing binary sequences with TOSE activity. A method is introduced to automatically select different controls of the generator for easy and precise tuning. Same technique is used to deterministically guide t he generator towards test sequences with improved fault coverage to pattern count ratio. This paper proposes a LP test compression method that allows the power envelope to be predictable, flexible and accurate using TOSE based LBIST. The proposed hybrid sc heme efficiently combines test compression with LBIST, where both techniques work to deliver high quality test.