HYBRID CMOS LOGIC TO IMPLEMENT HIGH SPEED AND LOW POWER 4-BIT CLA ADDER

Accuracy and speed of any digital system is greatly dependent on the performance of resident adders. Carry Look Ahead Adder overcome the disadvantage of large propagation delay in Ripple Carry Adder but consumes high power due to large number of gates involved in carry generation circuitry. However due to continuous evolution of portable technology with limited battery power supply, low power and high throughput VLSI systems are in great demand. This paper presents implementation of low power and low propagation delay CLA Adder, as compared to existing designs, using Hybrid CMOS Logic. Comparison between Hybrid Logic and other logic styles is also presented.