Modified Booth Multiplier with FIR Filter

In this paper, we develop a new methodology for designing a lower-error and area efficient 2’s complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error compensation bias is realizable, constructing low-error fixed width Booth multiplier is area and time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to FIR filter. The simulation results show that the performance is superior than by using the direct-truncation fixed-width Booth multiplier.