Realization of Low Power Multiplier Design Based on Vedic Iteration TechniqueJournal: International Journal of Science and Research (IJSR) (Vol.9, No. 12)
Publication Date: 2020-12-05
Authors : Charu Verma; Ankit Kumar Singh; Ravi Tiwari;
Page : 1014-1017
Keywords : Vedic Mathematics; Urdhva-triyakbhyam sutra; FPGA;
Vedic mathematics is the ancient methodology of the Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formula). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high-speed low power processes is reported in this paper. Simple Boolean logic is combined with Vedic formula, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensures substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Both Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectra using standard 90nm CMOS technology. The propagation delay of the resulting 32x32 multiplier was only ~1.06 us and consumes ~132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones.
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