Design of Coarse Grain Architecture for DSP Application?

CGRAs consist of an array of a large number of function units (FUs) interconnected by a mesh style network. In stream-based applications, such as telecommunications, data encryptions, and signal processing are the workloads in many electronic systems. In these applications, the real-time constraints often have stringent energy and performance requirements. The application-specific integrated circuits (ASICs) become inevitably a customized solution to meet these ever-increasing demands for highly repetitive parallel computations. In this project proposing a coarse grain architecture and mapping of some DSP Algorithm.