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PERFORMANCE EVALUATION OF 4:1 MULTIPLEXER USING DIFFERENT DOMINO LOGIC STYLES
Journal: International Journal of Electronics and Communication Engineering and Technology (IJECET) (Vol.7, No. 4)Publication Date: 2016-08-25
Authors : Mukherjee D.N. Panda S.and Maji B.;
Page : 20-31
Keywords : Multiplexer; Low power; Speed; PE logic techniques; domino keeper technique; Inverter feedback technique.;
Source : Download Find it from : Google Scholar
Abstract
In the present scenario the low power and the speed play an important role in the field of digital VLSI circuits. The main objective of this paper is to design and implement of power consumption of 4:1 Multiplexer in various logic styles and compared in terms of power consumption and propagation delay. The results of this paper are simulated on the EDA tanner tools realized in 0.25-micrometer technology.
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Last modified: 2018-04-05 19:36:25