INTEGRATE & FIRE NEURON AND DIFFERENTIAL PAIR INTEGRATOR SYNAPSE INTERCONNECTION– COMPUTATION & ANALYSIS IN 180nm MOSFET AND CNFET TECHNOLOGY

Neuromorphic Engineering deals with hardware implementation of the biological neural networks in silicon. The hard ware analog VLSI circuits and systems, specifically within the imposed constraints of low power and area, find applications in implants and prosthetics. The silicon neurons and synapses form the basic building blocks of these networks. The biological plausibility of the neuromorphic networks largely depends upon the efficiency of their basic building blocks in terms of area and power consumption. It is thus necessary for the basic components to be compact and highly energy efficient if the magnificence of biological networks is to be attained in these hardware neuromorphic networks. The silicon neuron and synapse circuits are largely benefitted, both in terms of area and power requirements, from the advancement in semiconductor technology with constant scaling of the MOSFETs. But in this era, with the approaching end to MOSFET scaling there is a quest to find a replacement for MOSFETs in the circuits which may carry forward the inheritance of Moore's law in future. The Carbon Nanotube Field Effect Transistors (CNFET) are one of the probable contenders capable of substituting MOSFETs in circuits owing to their superior electrical properties, lower power requirements as compared to MOSFETs. In this works we have transferred a low power Integrate and Fire neuron circuit and a differential pair integrator static synapse circuit, already reported in literature, to 180nm MOSFET technology. The circuit simulations are carried out using Cadence software toolset for varying circuit parameter values to study and analyse their effect on the outputs. The same circuits are then ported to CNFET technology and simulated using HSPICE software tool for variable circuit parameter values to ensure the viability of CNFET technology in implementation of analogVLSI neuromorphic circuits. The differential pair integrator circuit is then connected to the Integrate and Fire neuron circuit and simulated in 180nm MOSFET as well as CNFET technology to investigate the communication and signal transfer between them. A comparison of power consumption in the circuits is carried out for all the simulation accomplished in 180nm MOSFET and CNFET technologyto ascertain the advantage of low power requirements of circuit implementations in CNFET technology.