Reducing Runtime of RSA Processors Based On High
Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.2, No. 11)Publication Date: 2013-11-30
Authors : Prabha N.;
Page : 3214-3218
Keywords : `ASIC implementation;
Abstract
Depends on various requirements the paper presents & optimized Rivest processor which satisfies circuit area, operating time. we also introduces 3 multiplier based data path using different intermediate data forms: 1) single form, 2) wide variety of arithmetic components. A total of 242 datapaths for 1024 radix. We can reduce the RSA runtime up to 0.24ms. As a result, the faste in less than 1.0 ms.
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