Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology

Phase locked loop (PLL) is one of the most crucial devices in almost all the electronic systems. PLLs are commonly used as clock generator or frequency synthesis in electronic applications. Phase noise represents the phase variations of a PLL output signal. Since Phase noise reflects the stability of the PLL systems it is considered the most important characteristic. For any electronic device in today world, it is considered best when it consumes low power and delivers maximum efficiency. To reduce the delay a PFD is designed using XOR and NAND gate. To increase the delay and decrease the frequency a Ring oscillator is designed with odd number of invertors and Noise immunity is increased by using a differential amplifier as it has double ended configuration which removes the common mode noise. The voltage control circuit is a cascade current mirror circuit. The PLL is designed using 45nm CMOS technology for high performance with 1.0 V power supply.