MINIMALLY BUFFERED DEFLECTION ROUTER INTERCONNECT WITH PREDICTION, IN NETWORK-ON-CHIP WITH FPGA IMPLEMENTATION

A conventional Network - on - Chip (NoC) router uses input buffers to store incoming packets which improves performance, but also it consume power significantly . While NoC with bufferless router design has shown reduction in area and power, and also offers similar performance to conventional buffered NOC designs for many workloads, compared to conventional buffered routers at high network load. This degradation is a significant problem for widespread adoption of bufferless NoCs.