CONGESTION CONTROL FOR SCALABILITY IN BUFFERLESS ON-CHIP NETWORKS WITH FPGA IMPLEMENTATION

Congestion is an important issue in networks and significantly affects network performance. The Scheduler acts as the central switch arbiter. The fundamental components in systems which contain shared resources are arbiters and a centralized arbiter is a tightly integrated design for its input requests. In this study, we propose a new centralized arbiter , which may be used in arbitration of a crossbar switch in NoC router, where , we design Islip arbiter using Islip scheduling algorithm with 2 - D mesh topology. More integration of system component into single die is allowed as possible by smaller feature sizes since fabrication technology continues to improve. The limiting factor for performance can be made by communication between these components except embodying the correct scheduling algorithm .