ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

An Efficient Way of Decreasing the Latency of Flip Flops with Floating Point Multiplier

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.2, No. 11)

Publication Date:

Authors : ;

Page : 3223-3226

Keywords : MFLOPS; Multiplier; CAD Design Flow.;

Source : Downloadexternal Find it from : Google Scholarexternal

Abstract

In this paper we proposed efficient implementation of floating point multiplier which is technology independent pipelined design. This also handles the case of overflow and underflow cases. This verified that they can decrease the flipflop latency over Xilinx flipflop core.

Last modified: 2014-11-12 22:56:42