An Efficient Way of Decreasing the Latency of Flip Flops with Floating Point Multiplier
Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.2, No. 11)Publication Date: 2013-11-30
Authors : G Lalitha Rani;
Page : 3223-3226
Keywords : MFLOPS; Multiplier; CAD Design Flow.;
Abstract
In this paper we proposed efficient implementation of floating point multiplier which is technology independent pipelined design. This also handles the case of overflow and underflow cases. This verified that they can decrease the flipflop latency over Xilinx flipflop core.
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Last modified: 2014-11-12 22:56:42